Chip Design Expert (RTL Design & Verification)

$100/hr

rate as listed

Workload: ~15–20 hrs/week
Engagement: Project-based
Location: Worldwide
Field: Engineering

Review realistic RTL design and verification tasks used to train and evaluate AI models. You will inspect specifications, reference solutions, testbenches and automated tests for correctness, fairness and difficulty.

The work

You will review hardware engineering tasks from end to end, including the specification, starting files, reference solution and automated tests. Typical assignments involve designing or repairing an RTL block, writing a testbench or assessing whether a proposed task accurately measures RTL reasoning.

What you will evaluate

You will verify that reference solutions pass, required behavior can be derived from the specification and tests distinguish correct designs from plausible but incorrect ones. Reviews should identify ambiguous requirements, answer leakage, weak coverage, false failures and shortcuts that make a task easier than intended. The platform screens for substantial industry experience, strong Verilog / SystemVerilog skills, experience with simulation and testbenches, and the ability to read and reason about Python test code. Experience with Icarus Verilog, Verilator, Yosys, cocotb, formal verification or AI benchmark review is nice to have.

Logistics

The role is remote and flexible, with an expected commitment of about 15–20 hours a week and an immediate start. The listing does not explicitly state that all work is asynchronous, so candidates should confirm any meeting or response-time expectations during onboarding.

Pay band: $100/hr

What they look for

5+ years of industry experience in RTL design or verification
Strong Verilog / SystemVerilog design and debugging skills
Simulation and testbench development experience
Ability to read and reason about Python test code
RTL task evaluation, specification review and test coverage analysis
Clear written technical feedback

Included with this listing

Interview prep — 10 questions

Matched to what this platform's screening actually measures. Answer each out loud in 60–90 seconds: claim → concrete example → implication.

What it tests: This verifies the required experience through concrete ownership of RTL, verification environments, debugging and sign-off work rather than relying on a job title.
A strong answer: Give a concise chronology with employers or project contexts, dates, block types and your direct responsibilities. Distinguish work you implemented or verified yourself from work owned by the wider team.
Where people lose it: Candidates lose points when they describe a chip or team at a high level but cannot identify the RTL, testbench, debug or review decisions they personally made.

Summary, eligibility guidance and screening preparation are prepared by Sidequest from the platform's posting. Check the source listing before applying.