What the work involves
You work inside Vivado the way you normally would — creating projects, writing or importing RTL, running synthesis and implementation, reading timing reports, poking at the IP Integrator, debugging with the simulator or ILA — while capturing the screen and documenting what you did and why. The output is not a tutorial. It is a record of authentic engineering decisions: which constraint you wrote, which timing path you chased, what the failure message actually meant, and how an expert would recognise that a model's answer is wrong.
Tasks typically arrive as prompts or scenarios, and you respond with a sequence of screenshots plus written reasoning. Some assignments ask you to evaluate model-generated answers about Vivado workflows and mark where they drift from what the tool really does — non-existent menu paths, misread timing summaries, TCL commands that fail in the current version.
What the platform screens for
- Proof of access. You must be able to open Vivado on a Windows machine today. Screen-share or a live screenshot is a routine part of the check.
- Real project history. Screeners probe for boards you have targeted, toolchain versions, and problems you solved — generic FPGA vocabulary without a specific device family or error message reads as thin.
- Display capability. Screenshots must exceed 2.5 megapixels, via a single high-resolution monitor or two side-by-side 1080p+ displays captured as one spanning image.
Logistics
Fully remote and asynchronous. Work is drawn from a queue rather than scheduled, so hours are flexible, but most contributors commit to a stated weekly minimum — commonly 10–20 hours — and pace matters more than availability at particular times. Observed pay for this listing is $45–55/hr; rates vary by task type and are not guaranteed. There is no license reimbursement: WebPACK or an existing seat on your own machine is on you.