What the work involves

This is evaluation work for engineers who have shipped firmware or RTL on hardware that someone actually paid for. Day to day you'll be handed engineering tasks and candidate solutions — an interrupt handler, a SPI driver bring-up sequence, a SystemVerilog module and its testbench, a HIL test harness, a flight software fault-response routine — and asked to judge whether the implementation is correct, robust, and feasible on real silicon. That means catching the race between an ISR and the main loop, the DMA buffer that isn't cache-coherent, the clock-domain crossing without a synchronizer, the timing assumption that holds in simulation and dies on the board.

The other half is authoring. You'll write technically rigorous problems with reference implementations, test cases, and explicit grading criteria — problems that are hard for the right reason, where the trap is a genuine system-level failure mode rather than a syntax puzzle. Written justification matters more than the verdict: a rating with a paragraph naming the specific failure mechanism and the conditions under which it manifests is the deliverable.

What the platform screens for

Mercor's screen is AI-led and heavily follow-up driven. It will pick one project from your history and drill: what was the part number, what was the clock rate, what did you see on the scope, how did you isolate it, what did you change. Ownership depth is the real filter — the listing asks for someone who was the responsible engineer through bring-up, verification, and deployment, not someone who reviewed a design doc. Recency matters too: at least three of your five-plus years should be hands-on rather than managing people who were hands-on.

  • Name your specialization clearly — embedded/RTOS, FPGA/RTL, flight software, or HIL/test automation — and answer from inside it
  • Expect to be asked what you'd reject and why, not just what you'd approve
  • Vague answers get re-asked; specific ones get a harder follow-up, which is the good outcome

Logistics

Fully remote and asynchronous, with flexible engagement structure — most contributors work part-time alongside a primary role, commonly 10–20 hours a week, though availability expectations vary by project. Observed pay for this listing is $100–120/hr, stated as observed and not guaranteed; rate and volume depend on the specific workstream and your demonstrated domain depth. Access to hardware is not required for the evaluation work itself, but the judgment you bring from having used JTAG, logic analyzers, and HIL rigs is the entire point of the role.